The present invention relates to timing control of signals between a system on chip (SoC, which may be referred to as SOC) architecture and a memory chip thereof, and more particularly, to a method for performing memory interface control of an electronic device, and an associated apparatus.
According to the related art, semiconductor chips may be put together and packed into the same package, in order to reduce the size of a printed circuit board (PCB) and/or the size of an electronic device. Taking the SoC architecture as an example, the semiconductor chips may comprise a SoC chip having some memory interface terminals near the four sides of the SoC chip, and may further comprise a random access memory (RAM) chip having some memory interface terminals near the four sides of the RAM chip. Based on the conventional design, the RAM chip may be put on the SoC chip, and the memory interface terminals of the RAM chip may be electrically connected to the memory interface terminals of the SoC chip through soldering. However, some problems may occur. For example, different lengths of paths may cause skew issues. More particularly, in a situation where the difference between the lengths of two paths reaches thousands of micrometers, for example, timing alignment may be very difficult. Thus, a novel method is required for enhancing memory interface control of an electronic device having multiple semiconductor chips that are packed together, in order to guarantee the overall performance thereof.